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The Microelectronics group at Draper consists of a small group of motivated engineers engaged in the development of analog/mixed-signal application-specific integrated circuits (ASICs). We enjoy the challenge of specifying and realizing ASICs from the ground up. We are looking to add new members to our team who are capable of specifying and architecting ASICs, designing circuits using the Cadence tool suite, leading tasks, and interfacing with other engineers in a highly collaborative environment.
1) MOS/Bipolar transistor-level design, including biasing and both large & small-signal operation
2) Comprehensive understanding of transistor architecture(s) for one or more of the following:
3) Design and simulation experience with Cadence front-end tools
4) Familiarity with either MOSIS or TAPO MPW runs
1) Experience with sensor-interface circuitry
2) Experience with back-end flow using either Cadence or Calibre tools
3) Top-level simulation & layout experience
4) Experience with MOS advanced nodes below 32nm
BS, MS, or PhD degree in a relevant technical field of study and five or more years of experience designing mixed-signal integrated circuits.