Principal Digital Verification Design Engineer

Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space exploration to biomedical engineering, lives often depend on the solutions we provide. Our multidisciplinary teams of engineers and scientists work in a collaborative environment that inspires the cross-fertilization of ideas necessary for true innovation. For more information about Draper, visit www.draper.com.

Our work is very important to us, but so is our life outside of work. Draper supports many programs to improve work-life balance including workplace flexibility, employee clubs ranging from photography to yoga, health and finance workshops, off site social events and discounts to local museums and cultural activities. If this specific job opportunity and the chance to work at a nationally renowned R&D innovation company appeals to you, apply now www.draper.com/careers.

Equal Employment Opportunity

Draper is committed to creating a diverse environment and is proud to be an affirmative action and equal opportunity employer.   We understand the value of diversity and its impact on a high-performance culture.  All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, disability, age, sexual orientation, gender identity, national origin, veteran status, or genetic information.   

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Draper’s Digital Design Team is seeking a motivated and experienced Principal Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern verification strategies to complex digital and mixed-signal designs in the areas of embedded security, cryptography, signal and image processing, navigation and communications.

You will develop verification approaches, author and execute verification plans, and use formal analysis tools. While leading verification teams, you will define the test-bench architecture and verification approach. You will be responsible for developing methodologies and defining processes used by verification teams. You will also have the opportunity to lead multi-disciplinary teams and learn, grow and contribute to a variety of projects. Join us as we develop the next generation of digital and embedded hardware platforms.

Duties and Responsibilities

• Develop verification and test plans
• Develop UVM Agents for proprietary buses
• Instantiate VIPs for industry standard buses
• Work in both block-level/chip-level UVM testbench environment
• Work with RTL designers to resolve simulation issues  
• Implement cover groups according to design requirements
• Work on code and functional coverage closures to achieve 100%
• Perform code reviews and to mentor junior engineers in the group

Required Qualifications:      

• BS degree with 15 years’ experience
• Fluent in SystemVerilog including SVA
• Recent experience with UVM/UVMF
• Familiarity with at least one major industry simulator (Questasim, Xcelium, VCS)
• Familiarity with at least one IEEE bus standard
• Experience with DDR3/DDR4, Amba Axi protocols 
• Firm grasp of constrained-random testing and coverage-driven verification
• Experience with formal analysis
• Practice using Python, Perl, Bash or other scripting languages
• Ability to work in a Linux environment
• Strong analysis and problem-solving skills

Security Requirement:     

• The ability to obtain a US secret clearance is required which requires proof of US citizenship
• Active secret clearance is preferred

Location: Can be Hybrid OR Remote